FPGA (Actel ProASIC 500K Family) based system for Phase demodulation
The system will receive two out of phase signals from a gyroscope.
1. Phase modulated signal
- Modulating signal of (0-100) Hz, 1V p-p.
- Carrier signal of 200Khz and its first and second harmonics, 1V p-p.
2. Sinusoidal carrier signal 200Khz +/- 10Khz.
 The output is the Phase difference between the signals with amplitude (0-20V) p-p.
The system has optional filtering for both the signals. Then the filtered Analog signals
are digitized using a dual channel 12-bit Fast ADC (AD10242BZ, sampling rate of up
to 40 MSPS). The digitized signals are fed to the FPGA, where all the signal processing is done and the modulating signal is extracted and fed to a 16-bit DAC (AD669) as the extracted signal is in digital form. There are level converters between FPGA-ADC and FPGA-DAC for converting the signal levels between the devices. The final output is the amplified signal obtained from the DAC.
For processing the digitized data following signal processing blocks are implemented in the FPGA in VHDL:
- Hilbert transform
- Complex multiplier
- FIR filter
- CORDIC
- Averager
For controlling the data flow between the above-mentioned blocks, there is an overall controller using
Finite State Machines (FSM). |
