| |
|
| |
Digital Signal Processing Products |
|
|
|
| |
General purpose, high computation power signal processing units:
WG-dspPORT is a series of electronic modules for high performance digital signal processing (DSP) applications.
These modules can either operate in association with a personal computer (PC) or function in a stand-alone mode for portable on-field applications. The series of modules offers perhaps the widest range of addon modes (serial / parallel ports/PCI bus), ADC & DAC performance specifications, extendable communications & user-friendly software to meet all the needs of an application engineer. All WG-dspPORT modules are shipped with necessary user interaction software and application. programming interfaces.
Typical applications:
- Implementation of radar, sonar and sodar signal processing systems and algorithms.
- Implementation of industrial analysis systems for vibration, balancing and universal testing.
- Speech recognition and synthesis system building, acoustic noise cancellation systems.
- Telecommunication systems such as advanced modems,telemetry.
- Real-time image processing algorithms for compression, pattern matching and enhancement.
- Industrial data acquisition and real-time processing/control.
- Research and development of DSP based algorithms.
- Education and training of DSP techniques.
|
| |
......................................................................................................................................................................................................................................................................Top |
| |
WG - dspPORT-1.1 |
|
|
WG-dspPORT-1.1 Parallel processing DSP module
- DSP processor :ADSP-2105, 12.5 MHz ;
- External RAM : 32 K words, zero wait-state ;
- Analog inputs : 8 (multiplexed + -5 volt) ; ADC resolution, speed : 12 bits, 100 KSPS ;
- Analog outputs : 1 (Buffered +-5 volt) ; DAC resolution, speed : 12 bits, 100 KSPS ;
- Communications : SPORT on DB-9 ; Parallel port on DB-25 ; Power supply : 230 VAC, 50 Hz
|
| |

Functional block schematic; WG-dspPORT-1.1 |
| |
.....................................................................................................................................................................................................................................................................Top |
| |
WG - dspPORT-2.0 |
|
| |
| DSP processor : ADSP-2105, 10 MHz; |
| External memory : 32 KW RAM & 64 KB EPROM; |
| Analog inputs : 8 (multiplexed + -5 volt); |
| ADC resolution, speed : 12 bits, 100 KSPS; |
| Analog outputs : 1(Buffered +-5 volt); DAC resolution, |
| Speed : 12 bits, 100 KSPS; |
| Communications : SPORT on FRC; Serial port on FRC; |
| Digital IO : Opto-isolated 8 bit I/O |
|
| |
.....................................................................................................................................................................................................................................................................Top |
| |
WG - dspPORT-3.0 |
|
| |
| Sound codec : AD1847; |
| Sampling speed : 48 KHz (max.); |
| Audio channels : Stereo LINE IN/OUT, MIC IN and AUX IN; |
| Sound ADC : 16 bit Sigma-Delta; |
| Communications : SPORT on DB-9 |
|
| |
.....................................................................................................................................................................................................................................................................Top |
| |
WG - dspPORT-4.0 |
|
| |
| Sound codec : AD1847; |
| Sampling speed : 48 KHz (max.); |
| Audio channels : Stereo LINE IN/OUT, MIC IN and AUX IN; |
| Sound ADC : 16 bit Sigma-Delta; |
| Communications : SPORT on DB-9 |
|
| |
Top |
| |
WG - dspPORT-5.0 |
|
| |
| DSP processor : ADSP-2106X, 40 MHz; |
| External RAM : Upto 4 MW; |
| Analog inputs : 8 (+-10 volt); |
| ADC resolution, speed : 16 bits, 200 KSPS; |
| Analog outputs : 8 (Buffered +-5 volt); |
| DAC resolution, speed : 16 bits, 30 MSPS; |
| Communications : SPORT on DB-9 ; Serial port on DB-9 ; LPORT on DB-9; |
| Digital I/O : 8 bits (TTL) |
|
| |

Note: 1 - N = 2M / 1M / 512 K /256 K |
| |
.....................................................................................................................................................................................................................................................................Top |
| |
WG - dspPORT-6.0 |
|
| |
| DSP processor : 2 ADSP-2106X, 40 MHz; |
| External RAM : Upto 8 MW; |
| Analog inputs : 2 (+ - volt); |
| ADC resolution, speed : 14 bits, 3 MSPS; |
| Analog outputs : 1(Buffered + -5 volt); |
| DAC resolution, speed : 16 bits, 30 MSPS; |
| Digital I/O : 16 bits (TTL); |
| Communication : SPORT on FRC, LPORT on FRC |
|
| |
.....................................................................................................................................................................................................................................................................Top |
| |
WG - dspPORT-8.0 |
|
| |
 |
| DSP processor : ADSP-2106X, 40 MHz; |
| External RAM : Upto 4 MW; |
| Analog inputs : 4 (+ - 5 volt); |
| ADC resolution,speed : 16 bits, 200 KSPS; |
| Analog outputs : 1(Buffered + -5 volt); |
| DAC resolution, speed : 16 bits, 30 MSPS; |
| Digital I/O : 8 bits (TTL); |
| Communication : SPORT on FRC; |
| LPORT on FRC |
|
|
|
|
|
| |
.....................................................................................................................................................................................................................................................................Top |
| |
WG - dspPORT-8.1 |
|
| |
|
|
| DSP processor : ADSP-2106X, 40 MHz ; External RAM : Upto 4 MW ; |
| Analog inputs : 2 (+- 5 volt) ; ADC resolution, speed : 14 bits, 10 MSPS ; |
| Analog outputs : 1 (Buffered +-5 volt) ; DAC resolution, speed : 16 bits, 30 |
| MSPS ; Digital I/O : 16 bits (TTL) ; Communication : SPORT on FRC ; |
| LPORT on FRC |
|
|

Fig.-1 Functional block schematic; WG-dspPORT-8.1
|
| |
.....................................................................................................................................................................................................................................................................Top |
| |
WG - dspPORT-8.2 |
|
| |
|
|
| DSP processor : Upto 6 ADSP-2106X, 40 MHz ; |
| External RAM : Upto 4 MW ; Digital I/O : 8 bits, (TTL); |
| Communication : SPORT, LPORT on FRC |
|
|
|
| |

Functional block schematic; WG-dspPORT-8.2 |
| |
.....................................................................................................................................................................................................................................................................Top |
| |
WG - addaPORT-1.0 |
|
|
General purpose and low cost analog I/O interface family for a PC. |
| |
.....................................................................................................................................................................................................................................................................Top |
| |
WG-radarPORT-1.0 |
|
| |
This is a radar target environment simulator, which can be used for checking the various signal processing algorithms.
WG-radarPORT-1.0 can generate various I, Q signals with programmable range bin clock rate, PRT/Doppler bin clock rate etc.
Technical specifications of WG-radarPORT-1.0: |
| |
| Signal Generation Logic: |
DSP processor based run time coding |
| Analog Outputs (I,Q): |
Two channels, 5 Volts / 2.5 Volts / 1 Volt |
Analog Output Resolution:
|
16 bit, 30 MSPS update rate |
Timing Signals:
|
Maximum 48, TTL/OC |
| Digital I, Q: |
Maximum 16 bit resolution for each channel |
| Digital Input: |
16 - TTL compatible |
| Power supply: |
230 V, 10%, 1 Phase, 50 Hz 3% |
| Temperature: |
0 - 40OC |
| Humidity: |
10 - 95% non-condensable |
|
| |
Key Features: |
| |
| Programmable Parameters |
| Range clock rate: |
Maximum 5 MHz. |
Range Bins:
|
20 to 4096 |
Doppler bins:
|
8 to 2048 |
PRT:
|
100 sec - 2 msec. |
Host Interface:
|
RS232C |
Synchronization:
|
Internal / external 10 MHz base clock (optional) |
| I-Q mode: |
Analog / Digital |
| Timing Signal: |
Maximum 48 [in analog IQ mode] |
| Timing resolution: |
200 nsec |
| Optional Modules: |
On-line noise addition |
|
Noise type- |
Gaussian, additive |
|
Clutter- |
as per user requirement |
| I - Q: |
Coded Biphase, Uncoded |
| Code length: |
8/16/32 bits |
Typical Applications:
- BITE for RADAR / SODAR
- Timing Signal Generator for RADAR / SODAR Controller
|
| |
.....................................................................................................................................................................................................................................................................Top |
| |
WG-dspPORT- A.0 |
|
|
 |
| |
Technical specifications of WG-dspPORT-A.0: |
| |
Processor:
|
AD14060-BF @ 160 MHz |
Computation Power:
|
480 MFLOPS peak |
| 320 MFLOPS Sustained |
Analog channels:
|
4 |
Input signal range
|
1.0V |
Anti-aliasing filter-
|
7th order Butterworth at each input |
Maximum sampling rate-
|
41 MSPS |
| Resolution- |
12 bits |
| FIFO depth per channel- |
1024 words |
| Analog output channels: |
1 |
| Analog output range- |
1.0V |
| Maximum update rate- |
30 MSPS |
| Resolution- |
16 bits |
|
Host interface options: |
RS 422, DPRAM |
|
Debug ports: |
RS422, : JTAG |
|
External interrupts: |
Global reset |
| Differential 2 interrupts (Configurable through CPLD) |
|
Digital outputs: |
16 (TTL) |
|
Digital inputs: |
8 (TTL) |
|
Memory: |
|
|
Boot memory- |
128 kB |
|
Application memory- |
1MB Flash |
|
ZWS SRAM- |
512kx32 bits |
|
Application reserved signals: |
Two flags directly from the processor |
| Two differential interrupts |
| Memory chip selects signal from the processor |
|
DMA ports: |
5 Link ports, 2 SPORT |
|
Interface connector: |
Euro and MIX EUR |
|
PCB Size: |
150 mm x 220 mm |
|
Operating temperature range: |
-40 C to +85OC |
|
| |
| Back to Products Page | |
| |
.....................................................................................................................................................................................................................................................................Top |